High Speed Synchronization Using Modified Pausible Clocking Method

Synchronizer proposed in the literature for transferring the data from asynchronous to synchronous blocks achieves zero probability of metastability using the pausible or stretchable clocking scheme. But their highest data transfer rate is limited by the delay in generating the consumed signal. To overcome this problem, a scheme which makes the maximum data transfer rate of these synchronizers to be independent of this delay is proposed in this paper. The efficacy of the proposed scheme is evaluated by implementing a synchronizer for transferring data from a 4 bit asynchronously pipelined ripple carry adder to 4-Data Flip flops in 90nm UMC process technology and studying the functionality through post-layout simulation. The proposed scheme results in a 75% higher data transfer rate and a 42% lower power-delay product (PDP) compared to the synchronizer using the conventional pausible clocking scheme. Power consumed and area overhead for the proposed scheme are also lower compared to synchronizers using the pausible bisynchronous FIFO and Brute force bisynchronous FIFO based technique. The proposed scheme is well suited for applications where the metastability failures are not acceptable.