Digital-to-Time Converter Gain Calibration with a Muxed Delay Locked Loop

Digital-to-time converters (DTC) have found increasing adoption in frac-N PLLs to compensate for the excess phase error caused by delta-sigma modulator (DSM). DTC gain has to be calibrated in order to achieve the intended compensation. Existing digital DTC calibration methods require various forms of time to digital conversion (TDC). In this paper a low complexity and area efficient analog DTC calibration method without the need for a TDC is proposed. It is based on a delay locked loop with an input-muxed phase frequency detector (PFD). The input clock signals to the PFD are muxed by the sign of the excess phase error from the DSM. This analog calibration method is functionally equivalent to the conventional sign-error Least Mean Square calibration methods implemented in digital domain. Circuit non-idealities including noise and phase offset can be mitigated. DTC gain calibration error <; 1% can be achieved in mixed-signal simulation.