Reconfigurable Parser for Software Defined Network L4 Ethernet Switch Chip

a reconfigurable packet parser suitable for an L4 Ethernet switch chip is proposed to satisfy the flexibility and versatility requirements of software defined network to hardware. It implements the basic fixed functions by fixed hardware while user-defined functions by reconfigurable logic in addition to programmable execution unit. Thus, it does not only enable users to define the protocols but also enables users to define the actions during parsing. Its highest packet throughput is 240M packets per-second. Its size is about 7.37 million gates.