A Novel Low Channel Resistance LDMOS with Planar and Trench Gates

A novel low channel resistance Lateral Double-diffusion Metal-Oxide Semiconductor (LDMOS) device with planar and trench gates is proposed and numerical simulated in this paper. The drift region of the device is based on the triple Reduced SURface Field (RESURF) and OPTimum Variational Lateral Doping (OPT-VLD) techniques, and the gate structure is improved to dual gates with a planar and a trench gates. The simulation results show that the gate channel resistance Rch and the specific on-resistance Ron,sp are reduced by more than 52.92% and 10.45%, respectively, in comparison with the conventional planar-gate triple RESURF OPT-VLD LDMOS device.