A 100Gb/s PAM-4 Receiver Analog Front-End

This paper describes an inverter-based receiver analog front-end design using T-coil technique implemented in a 40nm CMOS process. The proposed T-coil can separate the capacitance of PAD and preamplifier itself, to achieve a total bandwidth enhancement ratio of 2.7. The proposed continuous time linear equalizer(CTLE) adopts a negative feedback loop to generate low frequency zero-pole pair to slower down the compensation slope. The simulation result shows that the transimpedance gain of the system is 76.5 dBΩ under the bandwidth of 37GHz. The input referred noise current in maximum gain mode is 2.3uArms.