Design and Performance Analysis of Transmission Gate Based 8T SRAM Cell Using Heterojunction Tunnel Transistors (HETTs)

Static Random Access Memory is a type of semiconductor memory that uses bi-stable latching circuitry (flip-flops) to store each bit. SRAM exhibits data reminisce but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered. The power consumption of SRAM varies widely depending on how frequently it is accessed. Several techniques have been proposed to manage power consumption of SRAM-based memory structures. A typical SRAM cell is made up of six MOSFETs.SRAM plays a substantial role in the world of microprocessors. As the world is craving for devices that are compact and portable, there is a need to reduce the size of SRAM that comprises about 70% of the SOC (System on Chip). Scaling is the one of the best techniques used in CMOS IC technology. While scaling down of the CMOS circuits, there arises a problem of high leakage losses. For solving this problem in SRAM cells, a transmission gate based 8T SRAM cell is used. The 8T SRAM cell is analogous to the 6T SRAM cell, the only exception being the 8T SRAM cell possesses full transmission gates which replace access pass transistors. In this work, the transmission gate based 8T SRAM cell to minimize the power consumption and losses is designed and implemented by using Heterojunction Tunnel Transistors (HETT) and the performance analysis is done with reference to conventional transmission gate based 8T SRAM Cell.