Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults

Gate-exhaustive faults address the fact that not all the defect mechanisms and behaviors are known in advance, and not all of them can be translated into fault models. Therefore, it is advantageous to ensure that a test set covers unexpected defects by exhaustive testing of gates or subcircuits. This paper observes that these properties make gate-exhaustive faults suitable for providing extra coverage for sites where coverage is missing because of undetectable target faults from other fault models. Undetectable faults result from logic redundancy, and leave circuit sites uncovered. To allow subcircuits to be considered as gates while avoiding the need to consider large numbers of faults, the gate-exhaustive approach is applied selectively. Instead of using all the input patterns of every gate, the iterative procedure described in this paper uses increasing numbers of input patterns of gates that include undetectable target faults in order to achieve a coverage goal for these faults. Experimental results demonstrate the extent to which it is possible to cover the sites of undetectable single stuck-at faults using tests for gate-exhaustive faults.