FPGA Based Interface Interlock Unit for Radar Power Sequencing

This research paper mainly focus on study of an Interface Interlock Unit (IIU) used in radar sub system for timely switching of power sequencing operations. Here mainly the IIU uses Field Programmable Gate Array (FPGA) as an integrated circuit and FPGA based IIU for radar power sequencer uses XilinxArtix7. IIU is an internal unit of Antenna Power Distribution unit (APDU) system which gives power to the antenna. Whenever the radar is used it is necessary to supply the power to the load. Therefore, this IIU card unit is realized on Xilinx based high end FPGA (Artix-7) for sequencing of proper ON and OFF operations to supply the required power. This system can protect from rush currents i.e whenever there will be presence of many loads to which the power to be supplied, by sequencing the system, it will be protected. IIU also helps in replacement of a particular load in case of damage occurrence.