Characterization and Modeling of Single Charge Trapping in MOS Transistors

Charging and discharging of single defects in MOS transistors seriously affects the performance of integrated devices. To identify the chemical structure of such defects density functional theory calculations can be carried out. For monitoring the impact of the defects on the device behavior the drain-source current through the device is measured and analyzed. The required data is typically recorded by applying voltage sweep measurements, noise/random telegraph noise (RTN) and measure-stress-measure (MSM) experiments. To explain the observed behavior and the impact of single defects on the electrical device characteristics physics-based defect models in combination with device simulators are often employed. After thorough calibration of the models employing detailed experimental data accurate time-to-failure estimations of MOS devices can be made. In this work the most frequently used electrical characterization techniques and advances in physical defect modeling applied to integrated transistors is discussed.