Critical Path Delay Improvement in Logic Circuit Operated at Subthreshold Region

Lower voltage as well as high-speed subthreshold logic circuits are becoming important factors in modern VLSI technology. At subthreshold region, the effects of the process variations and the diminished ratio of active current to ideal current can introduce timing errors. These timing errors are responsible in the vandalism of the working capacity of the circuits operated at subthreshold region. An increase in propagation delay is observed when the threshold voltage of MOSFET is more than the supply voltage. This paper proposes a circuit to reduce the timing errors keeping the energy consumption to minimum amount. The proposed circuit uses a multiplexer implemented using transmission gates, to be used in the longest delay path of the logic circuit which is operated at subthreshold region. Forward body biasing notion is used to lower the MOSFET's threshold voltage and is incorporated in the proposed circuit, thus, reducing the switching time of the MOSFETs. The proposed circuit is implemented using Cadence Virtuoso at 45 nm technology and compared with the circuit studied from literature survey. The supply voltage for the combinational circuit and the proposed circuit and the D flip-flop was 287 mV. The forward body biasing voltage V
_SB
for NMOS and PMOS MOSFET was equal to 287 mV. The proposed circuit is applied to the longest delay path of the 64-bit ripple carry adder operated at subthreshold region and the switching delay for high going and low going transition are measured and are reduced by 48.14% and 26.60% respectively. Also, the slope of transition of the output signal has been increased by 53.08% & 8.14% for rise and fall respectively. The total propagation delay diminished by 30.12% as compared to existing technique. The energy per cycle and energy-delay product (EDP) turned down by 33.10% and 53.31 % respectively, over the existing technique.