Design For Test of Radiation-Hardened SOC

At present, with the rapid development of space application technology, the radiation capability of SOC in space equipment is becoming more and more important. This brings new challenges to the Design For Test (DFT) design of radiation-hardened SOC. This paper introduces the DFT design method of a radiation-hardened SOC. This method can not only test the output of all registers and Static Random Access Memory (SRAM) cells when SOC is exposed to radiation sources, but also test the storage results of Triple Modular Redundancy (TMR) or Error Detection And Correction (EDAC) cells separately. The DFT design has been applied to radiation experiments and wafer test of radiation-hardened SOC, which greatly improves the test efficiency.