CNTFET Based Circuit Design for Improved Performance

Carbon Nanotube Field - Effect Transistor (CNTFET) is considered to be one of the promising devices to replace CMOS. The performance of CNTFETs mainly depend on device parameters such as number of tubes, pitch and nanotube diameter. A number of parameters must be considered for the design of the CNTFET based circuit including CNT diameter, pitch, and optimum number of carbon nanotube. In this work a design guideline based on the ratio of ON current to effective gate capacitance of CNTFET is presented to optimize circuit performance. A method referred to as Parallel Transistor Stack (PTS) is used in this paper to optimize power delay product (PDP) of the CNTFET based circuits. The simulation results obtained using HSPICE show that CNTFET based circuit design using PTS technique results into significant reduction in PDP of basic logic gates.