Defect Location and Physical Analysis in Chip-on-chip Device

The failure analysis (FA) case of devices with short defect is illustrated in this paper. First, X-ray microscopy reveals the device package to be a chip-on-chip (CoC) type package. Lock-in thermography (LIT) was then used to locate the short position, including its XY position and Z-depth (upper or lower die). Subsequently, three-dimensional (3D) X-ray was applied to clarify the connecting relationship between the failed pin and the bonding wire, further confirming whether the defect was on the upper or lower die. To verify the defect location, the devices were decapped and the short defect was confirmed by using optical beam induced resistance change (OBIRCH) and focused ion beam (FIB). The case study in this paper demonstrates the application of several FA techniques used for advanced packaging device and provides references for the defect location and physical analysis of similar device.