A Novel Method for Characterizing Temperature Sensitivity of Silicon Wafers and Cells

In this paper, we present a novel method to obtain temperature dependent lifetime and implied-open-circuit voltage (iV
_OC
) images of silicon wafers and solar cells. First, the method is validated by comparing the obtained values with global values acquired from lifetime measurements (for wafers) and current-voltage measurements (for cells). The method is then extended to acquire spatially resolved images of iV
_OC
temperature coefficients of silicon wafers and cells. Potential applications of the proposed method are demonstrated by investigating the temperature coefficients of various regions across multi-crystalline silicon wafers and cells from different heights of two bricks with different dislocation densities. Results indicate that dislocation clusters in wafers display both high and low temperature sensitivity. Reduced temperature sensitivity is exhibited by wafers from the top of the bricks compared to wafers from the bottom. This may suggest that some of the disadvantages of wafers from the top of the brick, which usually suffer from higher impurity concentration and therefore lower performance at room temperature, can be suppressed at higher temperatures.