A Real-time AD-Census Stereo Matching based on FPGA

In this paper, we present an environment for the acquisition of a flight image of drone and design an stereo matching accelerator based on FPGA(Field Programmable Gate Array) to acquire depth information at real-time from acquired images. The acquisition of the flight images of drone uses a stereo camera (ZED) and Jetson TX2 board environment. The obtained binocular image can acquire depth information in real time through a stereo matching accelerator. Stereo matching operations have large computational complexity and require hardware acceleration. In this paper, we design an FPGA based stereo matching accelerator. Accelerators implemented AD-Census stereo matching algorithm and Box Filtering cost aggregation function at high speed. Census cost calculation method uses 9×7 filter, and cost aggregation function uses 15×15 filter. In order to reduce the internal memory usage, a cost aggregation function with parallel operation is implemented and a dynamic fixed point operation method is applied in order to reduce the amount of computation block usage. As a result, the 480×270 resolution image on the KU040 FPGA board showed 41fps performance at 100MHz clock operating speed.