Design of an Area Efficient and High-gain CMOS Instrumentation Amplifier for VLSI Applications

In the present work, a new and improved CMOS instrumentation amplifier has been discussed for VLSI application. Low power differential amplifier and operational amplifier have also been designed here. Instrumentation amplifier has generally been preferred due to its easy gain changeability process. The designed CMOS instrumentation amplifier revealed satisfactory results in terms of gain, common mode rejection (CMRR), power consumption. On analysis, the proposed CMOS instrumentation amplifier shows a gain of 95.59 dB, CMRR of 108.4dB. On the other hand, Gain bandwidth is measured to be 3.95 MHz and power consumption of 4.85mW. The layout of the proposed instrumentation amplifier occupies an area of 34.74um*37.5um. The proposed circuit has been tested at 1.8V and the simulation has been carried out with the help of cadence analog design environment with UMC 90nm technology.