Design and Implementation of a high speed 4bit ALU using BASYS3 FPGA Board

An Arithmetic Logic Unit (ALU) is an integral part of a computer processor. It is one of the most frequently accessed modules in a CPU and is utilized during most instruction executions. It has the capability of performing no. of different arithmetic and logic operations such as addition, subtraction, multiplication, bit-shifts and different logic operations. This paper primarily deals with the construction of Arithmetic Logic Unit (ALU) using Xilinx VIVADO 2016.2 and implement them on Field Programmable Gate Arrays (FPGAs) to analyze the design parameters. The main objective of designing the ALU is to develop algorithms in order to achieve an efficient utilization of the available hardware. The measures of the efficiency of an algorithm are speed improvement, less power consumption and better utilization of ALU. In this paper, we have simulated and synthesized the various parameters of ALUs by using VERILOG on Xilinx Vivado2016.2 and BASYS3 FPGA board
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