An UWB 18.5 GS/s Sampling Front-End for a 74 GS/s 5-bit ADC in 22nm FDSOI

This paper presents the design of an ultra-wideband buffered front-end sampler (T&H) operating at 18.5 GS/s. The linear sampler, intended for a 5-bit 4x time-interleaved (TI) flash ADC, is realized in a 22 nm FDSOI (FDX) CMOS process. It comprises an ultra-low jitter limiting clock path and a PMOS-NMOS source follower T&H maximizing the linearity and isolation as well as enhancing the effective sampling bandwidth. The frontend takes advantage of the flipped-well forward-biasing process option lowing the transistor threshold voltage by 75 mV/V to achieve a differential input range of 600 mV
_p-p,diff
while using a dual 1.2 V and 0.9 V supply voltage. The frontend exhibits asampling bandwidth of more than 40 GHz across corners (worst case SS, T = 120°C), achieving a SFDR and SNDR of better than 41 dBc and 38 dB respectively at the fourth Nyquist zone (fin = 37GHz). The total power consumption is only 75mW of which 10 mW is consumed by the entire clock path.