A New Hardware Friendly 2D-DCT HEVC Compliant Algorithm and its High Throughput and Low Power Hardware Design

This paper presents a hardware-friendly algorithm to maximize the throughput of the Discrete Cosine Transform (DCT) of the High Efficiency Video Coding (HEVC), together with its hardware design. The Fast DCT (FCT) algorithm is based on the Cooley-Tuckey algorithm for the Fast Fourier Transform (FFT) with pre- and post-processing required to maintain the compliance with the HEVC. The resulting algorithm allows high throughput while maintaining low power dissipation. The designed hardware was synthesized for a 45-nm Nangate technology and it reaches a throughput of 81.28GSamples per second when consuming 12.33mW. Such energy efficiency and throughput surpass all related works in the literature.