Low Power, 11.8 Gbps 27-1 Pseudo-Random Bit Sequence Generator in 65 nm standard CMOS

This work presents a low power, 2
⁷
-1 pseudo-random bit sequence (PRBS) generator with data rates up to 11.8 Gbps in a standard 65 nm CMOS process. The proposed PRBS generator is designed with full-rate to reduce the circuit complexity and decrease power consumption. Furthermore, low power operation is achieved by optimization of the D flip-flops (DFF) circuit and the asynchronous XOR structure. All of the circuit are based on current-mode logic (CML). From the post-layout simulation results, it consumes 73 mW from a 1.2 V supply, and achieves a figure of merit (FOM) of 0.88 with peak-to-peak jitter of 5.5 ps.