A Scan Register Based Access Scheme for Multilevel Non-Volatile Memristor Memory

The memristor, an emerging non-volatile memory (NVM) device, has garnered widespread attention as a candidate device of choice for reconfigurable logic or memory systems due to its nanoscale dimension, scalability, multi-bit storage, and CMOS compatibility. This work provides a means for sequential access of memristors to configure or extract multi-bit information stored in a reconfigurable electronic integrated system. The proposed scheme uses two scan registers interchangeably to separate and parallelize the programming/reading and shifting in/out of data bits. To outline the utility of the scheme, scalability and energy analysis are provided.