Effect of lithography on SOI, grating-based devices for sensor and telecommunications applications

We demonstrate how lithography smoothing and proximity effects affect the performance of silicon-on-insulator devices that include grating-based, contra-directional couplers (contra-DCs). Using lithography models developed for CMOS-compatible, deep ultraviolet lithography processes, we predict and verify the spectral responses of fabricated contra-DC test structures. These verified models are then used to simulate and analyze the effects of lithography on the performance of a microring resonator with an integrated contra-DC, as regards the device 3-dB bandwidth (BW), insertion loss (IL), and adjacent side mode suppression ratio (SMSR). We demonstrate how the corrugation profile of the contra-DC is affected by smoothing and the inner and outer corrugation depths are reduced due to proximity effects. We show that, if the effects of lithography are not taken in account during device design flow, large discrepancies result between the predicted "as-fabricated" and "as-designed" device performance. Specifically, we demonstrate how the BW is reduced from 47 GHz to 21 GHz, how the IL is increased from 0.5 dB to 5.8 dB, and how the adjacent SMSR is reduced to 26 dB. We also establish that it is possible to use the lithography models to compensate for lithographic effects during device design flow and layout and to design a contra-DC in which the as-fabricated device performance metrics matches the target/expected as-designed performance metrics.