Stacking SiO2/ High-$K$ Dielectric Material in 30nm Junction-less Nanowire Transistor Optimized Using Taguchi Method for Lower Leakage Current

This paper reports the use of a stacking silicon dioxide (SiO
₂
)/ high - κ dielectric material in 30 nm junction less gate all around (GAA) nanowire transistor as an alternative approach to reduce the leakage current. The GAA nanowire transistor was optimized using L9 Taguchi method, simulated and characterized using SILVACO. Three types of high - κ dielectric materials are evaluated, namely hafnium oxide (HfO
₂
), aluminium oxide (Al
₂
O
₃
) and zirconium oxide (ZrO
₂
). Through simulation, it found that using stacking SiO
₂
/ high - κ dielectric significantly showed the reduction in leakage current by two (2) decades for ZrO
₂
with minimum effective oxide thickness of 1nm inline with targeted data from International Roadmap for Devices and Systems (IRDS). The use of GAA nanowire junction-less transistor with stacking SiO
₂
/ high - κ dielectric technique provide ways to minimize the well - known drawback associated with the short channel effect particularly the leakage current.