Programmable Local Clock SET Filtering for SEE-Resistant FPGA

This brief presents a new clock-related
Single-Event Effect
(SEE) mitigation method for
Field Programmable Gate Arrays
(FPGAs). SEEs are most likely to happen in harsh environments, such as space, and are decently mitigated with
Triple Modular Redundancy
(TMR). However, clock tree triplication has a high cost for FPGAs; it reduces the total amount of usable clocks and introduces uncontrolled skew variation. Therefore, we propose to instantiate a
Programmable Local Clock Filter
(PLCF) close to TMRed sequential elements to locally triplicate the clock and filter the SEEs coming from the clock tree. The PLCF mitigation method has demonstrated 100% resilience to SEEs, which target either the clock tree or the PLCF’s logic. Thus, PLCF represents the first programmable clock-related SEE mitigation method and proposes a promising alternative to the state-of-the-art technics applied to FPGAs’ fabric.