I. Introduction
In order to achieve faster data transmission rates, signals with large bandwidth and high peak-to-peak ratio (PAPR) are used. This kind of signal requires the power amplifier (PA) to maintain high efficiency at its power back-off (OBO) level. Traditional PAs such as class-J [1], class-F [2], etc. often can only obtain high efficiency at their saturation level. In order to enhance the ability of the PA to efficiently amplify high PAPR signals, several load modulation PA architectures have been proposed. Load modulation PA architectures such as Doherty [3], out-phasing [4] can maintain high efficiency at their OBO level. Among them, Doherty PAs (DPAs) are widely used in base stations due to their simple topology and low cost. However, the traditional DPA has narrow bandwidth due to the limitation of the load modulation network [5]. Recently, a promising load-modulation architecture, called load-modulation balanced PA (LMBA), has been proposed [6]. This architecture introduces an additional PA branch into the isolated port of the coupler in a balanced PA in order to realize the modulation of the load impedance, thereby yielding an excellent bandwidth advantage [7]. However, these LMBA arrangements can often only achieve an OBO of 6 dB [8]. In order to enhance the OBO performance, several improved works combining the DPA and LMBA architectures have recently been proposed, called DPA-like [9], pseudo-DPA [10], or balanced-DPA [11] which can achieve higher OBO in a wide frequency band. These combined PA types all need an additional PA branch to achieve load modulation in a wide bandwidth, whose topology is shown in Fig. 1(a). Additionally, the PA branches in these PA architectures use unequal sizes of transistors to achieve high OBO. Consequently, this greatly increases circuit complexity, and meanwhile the use of transistors of different sizes can result in underutilization of PA current consumption. In [12], [13], digital techniques are applied to simultaneously realize wideband and high back-off, but these methods would lead to more complicated circuits and higher costs compared to pure analog techniques.
PAs topology (a) previously reported PAs [6]–[11] (b) proposed PA.