Single Bit-Line Differential Sensing Based Real-Time NVSRAM for Low Power Applications

In this brief, we present a novel single bit-line differential programming scheme for 4T-2R NVSRAM. The NVSRAM presented in this brief not only uses an unconventional scheme of using differential sensing using a single bit-line, without the use of access transistors, but also leads an alternative transistor sizing approach for sizing the access and pull down transistors to improve write margins. The NVSRAM design used in this brief constitutes of two 3nm thick HfOx based OxRAM devices and four transistors designed at 90 nm CMOS technology node. The cell design is implemented for real-time non-volatility rather than last-bit non-volatility. Detailed analysis of the proposed single bit-line technique with parallel RRAM device programming scheme is presented in comparison to the previous NVSRAM programming schemes used for similar 4T-2R NVSRAM bit-cells.