M-PSK Demodulator With Joint Carrier and Timing Recovery

In this brief, we propose a new digital receiver for Phase-Shift Keying (PSK) modulation based on the integration of the conventional digital Costas Loop circuit with a new timing recovery method. The timing recovery is applied to the PSK demodulator using an Iterative Learning Control (ILC) law and it is based on the minimization of the intersymbol interference using only one sample per symbol. The main advantage of the proposed timing recovery method is the insensitivity to frequency offsets which results in improved performance and robustness of the Costas Loop circuit. Experiments comparing a conventional receiver (cascade of Costas Loop and Early-Late Timing Synchronizer) to the proposed receiver in scenarios characterized by low signal-to-noise ratios and large frequency and phase errors, show that the time needed to reduce the errors of the proposed receiver is seven times smaller than the conventional receiver. Moreover, the impact of the proposed method on the necessary hardware resources (area and power consumption) is negligible.

I. Introduction

The performance of a digital communication system is very dependent on carrier and symbol recovery, which are usually performed by the cascade of a carrier recovery subsystem and a symbol recovery block [1], [2]. In M-ary Phase Shift Keying (M-PSK) suppressed carrier modulation schemes, these operations are usually performed using closed-loop systems such as the Costas Loop for the carrier recovery [3]–[5], and the Early-Late or the Mueller and Müller or the Gardner timing synchronizers for the symbol recovery [6]–[8]. The key parameters are the recovery time, also known as lock-in time, and the capability to operate in noisy environments.