Dynamic Read Current Sensing With Amplified Bit-Line Voltage for STT-MRAMs

This brief presents a novel sensing approach for spin-based memories that augments the read sense margin and improves read decision failure without deteriorating read disturb by changing the read current dynamically according to the bit-cell state. The proposed sensing circuit consists of three main sub-circuits: 1) the bit-cell; 2) bit-line amplifier; and 3) a standard current-latch sense amplifier. The bit-line amplifier is a basic amplifier with positive feedback connection to achieve higher sense margin with dynamic read current. As a result, the significant increase in the sense margin eliminates the effect of the sense amplifier offset on read decision failure. Monte Carlo simulations in 45 nm demonstrate that the proposed sensing scheme improves the read bit error rate (BER) by more than one order of magnitude compared to the conventional voltage sensing scheme with a cost of 0.3% array area overhead and 3% energy penalty. Moreover, quantitatively compared with some of the state-of-the-art sensing schemes, the proposed scheme achieves a better area-energy-robustness trade-off.