A 12.8-Gb/s Quarter-Rate Transmitter Using a 4:1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner

This brief presents a 12.8-Gb/s quarter-rate transmitter for DDR interfaces. The 4:1 serialization required in a quarter-rate transmitter is performed by an overlapped multiplexing driver containing four unit drivers. Two of four unit drivers output two identical 1UI full-rate DQ signals simultaneously and these signals are merged while they perform final serialization. This reduces the I/O capacitance. Correct timing of this serialization process is maintained by adaptive alignment of the four phases of the clock signal. Implemented in a 55-nm CMOS technology, single-ended output swing of this transmitter is 400~600 mVpp, and it has an energy efficiency of 1.8 pJ/bit.