A 5.3-ps, 8-b Time to Digital Converter Using a New Gain-Reconfigurable Time Amplifier

Time amplifiers (TAs) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18-μm CMOS technology. Using a supply voltage of 1.2 V, the proposed TDC consumes 1.1 mW at 30 MS/s throughput.