A New Clock Phase Calibration Method in High-Speed and High-Resolution DACs

Current steering digital-to-analog converters (DACs) are well suited for high-resolution, high-speed applications. A serious design challenge is brought by the requirement of solving the setup/hold time violations problem between the output data from the digital clock domain and the analog clock under different process, voltage, and temperature conditions, and simultaneously maintaining high spectral purity of the analog clock. This brief presents a mixed-signal system to detect and correct setup/hold time violations for the critical analog clock in highspeed and high-resolution DACs. A power-efficient, novel 4-bit flash analog-to-digital converter, designed with a new architecture and reference adaptive generation technique while keeping overhead cost low, is proposed in this brief. The detection and correction circuit, together with a 13-bit 2.4-GHz DAC, is implemented in a 0.18-μm CMOS technology. The measured spurious free dynamic range and the output spectrum demonstrate the effectiveness of the proposed method. The combined clock phase calibration circuit not only improves the yield of DAC, but also increases the maximum allowable clock frequency for high-resolution DACs, which is especially advantageous for high sampling frequency design.