A Sizing Methodology for Rise-Time Minimization of Dickson Charge Pumps With Capacitive Loads

A novel sizing methodology for Dickson charge pumps with pure capacitive loads is presented. The methodology is based on dynamic analysis to minimize the rise time of the charge pump up to 25% under a given circuit area. The methodology is validated through the implementation of a six-stage charge pump-based driver in 180-nm standard low-voltage CMOS technology. The driver is used for the excitation of ultrasonic transducers with 34 V at a resonance frequency of 220 KHz. A rise time of only 512 nS is achieved. The driver consumes 10.6 mA drawn from a 5-V supply at a pumping frequency of 50 MHz and occupies an area of 0.2 mm
²
.