Accurate Estimation of CMOS Power Consumption Considering Glitches by Using Waveform Lookup

Gate-level power estimation methodologies are often considered as a sign-off level reference for digital circuit design. Nevertheless, when gate delays and related effects like glitches are taken into account, commercial state-of-the-art gate-level power estimators show surprisingly large estimation errors. Following an analysis of factors causing these inaccuracies, a novel gate-level power estimation approach is proposed, which combines lookup-based macromodels with the accuracy of analog signal waveforms and achieves significantly better results under the influence of glitches.