I. Introduction
Capacitance mismatch is a critical issue that affects the behavior of analog and mixed signal circuits, such as data converters and switched-capacitor (SC) filters. Estimating and measuring capacitance mismatch is crucial in the design of high-performance integrated circuits (ICs). In this brief, two figures of merit (FoMs) are adopted to estimate the capacitance mismatch in a given layout. These FoMs are presented in Section II and are used to compare different layouts in a test chip fabricated in a CMOS 0.35- process.