A 250- $\mu\text{W}$ 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications

This brief presents a fast-lock 2.4-GHz fractional-N phase-locked loop (PLL) for ultralow-power applications. To minimize the power consumed by all the other circuits except for the main oscillator, we propose a master–slave PLL structure in which a low-frequency master PLL is followed by a slave injection-locked oscillator operating at high frequency. A frequency-error compensation circuit is also implemented in the slave oscillator to eliminate possible drift in the free-running frequency. With a fractional-N coarse-lock unit in the master PLL and a fine frequency initialization unit in the slave oscillator, the PLL supports two fast-lock modes: 1) start-up locking from deep-power-down mode and 2) instantaneous relocking from standby mode. The implemented PLL in 65-nm complementary metal-oxide-semiconductor (CMOS) consumes 250
$\mu\text{W}$
from a 0.8-V supply, demonstrating a power efficiency of 0.102 mW/GHz. The PLL performs the two fast-lock operations with lock times of less than 22
$\mu\text{s}$
from deep power down and 1
$\mu\text{s}$
from standby, respectively.