A 0.5-V, 1.47- $\mu\hbox{W}$ 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation

A 13-bit successive approximation analog-to-digital converter (ADC) is presented for an ultralow-power sensor interface. Capacitor error compensation is achieved by swapping the roles of two identical capacitor banks in a digital-to-analog converter. The ADC is implemented in a standard 0.13-
$\mu\hbox{m}$
CMOS. With a single supply voltage of 0.5 V and a rail-to-rail conversion range, the ADC dissipates 1.47
$\mu\hbox{W}$
at a sampling rate of 40 kS/s. It shows a figure of merit of 17.9 fJ/conversion-step with an effective number of 11.0 bits.