I. Introduction
THE increasing demand for signal bandwidth and dynamic range in wired and wireless applications is leading to a higher demand of wideband high-resolution analog-to-digital converters (ADCs). Continuous-time delta–sigma ( ) ADCs are good candidates to fulfill these requirements [1]. In order to compensate for the low oversampling ratio (OSR) required in wideband applications, high orders of noise shaping combined with multibit quantizers are needed. In addition, by decreasing quantization noise, multibit quantizers improve modulator stability and increase its robustness against clock jitter. To take into account the inherent time response of the quantizer, a delay must be inserted between the output of the modulator and the input of the main feedback digital-to-analog converter (DAC), as shown in Fig. 1. For stability, this delay must be compensated. While most of the realizations use a delay of half a clock period [2]– [5], a compensation technique that allows an excess loop delay up to have been proposed in [6]. In low-speed applications, the loop delay allows adding a dynamic element matching (DEM) circuit to correct the mismatch-induced noise and distortions of the main multibit feedback DAC, which severely degrade the resolution. The data weighted averaging (DWA) technique is most often used because it offers a good tradeoff between hardware complexity and performances compared with other DEM techniques. However, in high-speed applications, the short available delay in the feedback loop puts a high constraint on the latency of the DWA circuit, which may be infeasible even in advanced CMOS nodes [2].
modulator with conventional excess loop delay compensation.