A 2.2μW PWM-Based Time-Domain Sensor Interface With 540mVpp Input Signal Range, 81.6dB SNDR and 80MΩ Input Impedance

This brief describes a power-efficient time-domain analog front-end (AFE) for autonomous sensor nodes. This AFE combines an input pulse-width modulator (PWM) and a gated ring oscillator (GRO) to facilitate low-voltage analog building blocks. The input PWM is implemented with pseudo-differential comparators for voltage-to-time conversion, achieving high input impedance and linearity concurrently. A non-equidistant GRO works at a fixed frequency and quantizes the PWM output in time domain, realizing the first-order noise shaping. The AFE is implemented in a
$0.18\mu \text{m}$
standard CMOS process. Clocked at 20kHz (500Hz bandwidth), the AFE achieves 81.6dB peak SNDR,
$540{\mathrm{ mV}}_{\mathrm{ pp}}$
input signal range, and 80M
$\Omega $
input impedance. The power consumption is
$2.2\mu \text{W}$
at 0.8V analog and 0.6V digital supply voltages, and these correspond to a Schreier FoM of 165.2dB. Finally, the AFE properties are verified through several types of sensors.