A 150-MS/s, 65-dB SNDR Fully Passive Bandpass Noise-Shaping SAR ADC

A fully passive bandpass (BP) noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) operating at a sampling rate of 150 MS/s is proposed. The proposed ADC structure is acquired by applying z to–z 2 transformation to a fully passive lowpass (LP) NS-SAR ADC structure. Therefore, the proposed BP NS-SAR ADC inherits most of the advantages of the existing NS-SAR ADCs and achieves high energy efficiency and hardware simplicity. The prototype ADC was fabricated in a 28-nm CMOS process and achieved a signal-to-noise-distortion of 65.44 dB with a bandwidth of 18.75 MHz. The power consumption is 2.184mW and the Schreier figure-of-merit is 164.8 dB.