A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Tap DFE

A digital clock/data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) and a calibration circuit is presented. This CDR circuit is fabricated in 40-nm CMOS technology and its active area is 0.1 mm
²
. For a channel loss of −10.31dB at 10GHz and a 20Gb/s PRBS of
$2^{7}-1$
, the measured bit error rate is less than 10
⁻¹²
. By the proposed calibration circuit, the measured high-frequency jitter tolerance is improved. The measured convergence time of the calibration circuit is less than
$5~\mu \text{s}$
. The power of this CDR circuit is 55.4mW at 20 Gb/s, and the calculated energy efficiency is 2.77pJ/b.