A 11-Bit 1-GS/s 14.9mW Hybrid Voltage-Time Pipelined ADC With Gain Error Calibration

This brief presents a 1GS/s 11bit hybrid voltage-time pipelined analog-to-digital converter (ADC) that leverages 1-bit dither correlation-based background calibration to correct the gain errors in residue amplifier (RA), voltage-to-time converter (VTC) and time-to-digital converter (TDC) caused by mismatch and the variations of process, voltage and temperature (PVT). A dual-supply two-stage no Miller-compensated residue amplifier (RA) with complementary inverter-based pre-amplifier, is applied to achieve high gain, high linearity and high bandwidth. The presented ADC occupies an active area of 0.083 mm
²
in 28 nm process. It achieves an SNDR of 58.2dB and an SFDR of 63.7dB after the calibration in the entire Nyquist zone, while consuming 14.9mW at 0.9/1.8V, contributing to Walden figure-of-merit (FoM) value of 22.1 fJ/conversion-step.