High Throughput Low Complexity and Low Power ePiBM RS Decoder Using Fractional Folding

This brief proposes a novel generalized Fractional Folding (FF) architecture for digital signal processing integrated circuits. With this new structure, a Fractional Folding based enhanced Parallel Inversionless Berlekamp-Massey (FF-ePIBM) Reed-Solomon Decoder is presented of which the number of processing element (PE) can be reduced to only one, resulting in ultra-low hardware complexity. The FF-ePIBM VLSI architecture can greatly reduce the hardware cost by about 60% compare to the fully expanded parallel ePIBM architecture. With FF-ePIBM architecture, syndrome calculation (SC) block and Chien search & error evaluation (CSEE) block are able to operate at a lower frequency resulting in about 14.8% power saving. A polyphase clock signal is needed in order to achieve fractional folding function according to specific fractional-factor. It is generated from Delay Locked Loop (DLL) at little or no extra cost in different SoCs. To maximize the throughput of decoder, pipelined architecture is adopted to optimize critical path delay. The RS (255, 239) decoder with FF-ePIBM architecture is finally implemented with 40nm CMOS technology. The synthesized results demonstrate that the decoder has a gate count of 12.9k and can operate at 3.1GHz to achieve a highest throughput of 24.8Gb/s and a best TSNT FoM value of 592 to this date.