A Triangular Common Subexpression Elimination Algorithm With Reduced Logic Operators in FIR Filter

Common subexpression elimination (CSE) technique is regarded as one of the popular methods to minimize the number of logic operators (LOs) in digital filter by eliminating the redundant occurrence of bit pattern. To this aim, this brief presents an innovative triangular CSE algorithm that generates FIR filters with reduced number of logic operators when compared to other CSE techniques in the literature. Supremacy of our design strategy has also been established in terms of logic operators and logic depths over a number of state-of-the-art techniques of recent interest. Simulation results have offered a noticeable average LO reduction when compared with other related algorithms. Supremacy of the proposed design has also been substantiated by implementing the filters on Cyclone IV FPGA chip.