QD-PFD: Quasi Dynamic Dead-Zone/Blind-Zone Free PFD With 23 nW–38 μW for 2 MHz–5 GHz Range and 150-ns Settling Time PLL Applications

The problem of the phase-frequency detector in the detection of a small phase difference during the reset cycle implies a blind zone that avoids immediate turn-on of charge-pump switches. This reduces the PLL acquisition speed. It also increases PLL energy consumption and degrades phase noise. In this brief, a completely symmetrical PFD without needing a reset cycle using latch input logic, logic mode, and quasi-dynamic (extra logic) transistors with no blind and dead zone is proposed. The proposed circuit is post-layout simulated at the circuit level in standard CMOS 180nm technology for [2MHz-5GHz]. The proposed PFD detects the linear phase difference between two inputs either in the range [
$- 2\pi $
,
$2\pi $
] or [
$-\pi $
,
$\pi $
] which mitigates the problem of missing clock edge and leads to faster PLL locking time. The proposed PFD consumes
$38~\mu \text{W}$
power at 5GHz frequency. Performing PFD in Process, Voltage, and Temperature (PVT) confirms the accuracy of PFD operation. Based on the detailed investigation of impactful paths and transistors on the phase noise, a new analytical approach is developed. The analytical and simulated phase noise values are equal to −165dBc/Hz and −167dBc/Hz at 1MHz respectively which confirms the developed model’s accuracy. Also, with the PFD test in the final block of PLL, a lock time of 150ns has been reached. The layout of the proposed PFD consumes an area of about
$308.34~\mu \text{m}~^{\mathrm{ 2}}$
in 180nm.