ASMPEC: Approximate-Sum-Based Mapping of Partial Products With Error Correction for Softcore Multipliers on FPGAs

In this brief, Approximate Softcore Multipliers are designed on Intel FPGAs to boost the energy efficiency of Error resilient Applications. Two partial products (PP) of a multiplier PP matrix are added approximately in a unique manner, to map on a six input ALM, in order to reduce the total resource utilization of the circuit. The carry generated in one column is also mapped with the sum of the next column for Error Correction. When compared to the state-of-art approximate multipliers, area savings of 6.25%-26.25% for 16-bit multipliers and minimum values of
$LUT\times CPD \times PDP$
for 8-bit multipliers, are achieved. Application based case study is performed on Convolutional neural networks (CNN), K-nearest neighbors algorithm (KNN) and Image multiplication.