A Capacitively Coupled Chopper Instrumentation Amplifier With Compensated Auto-Zeroed DC Servo-Loop for Neural Signal Recording

This brief presents a capacitively-coupled chopper instrumentation amplifier (CCIA) with a compensated auto-zeroed (CAZ) dc servo-loop (DSL) for neural signal recording. The proposed CAZ technique samples the low-frequency feedthrough noise via the DSL that appears at the output of CCIA, and compensates it in the integrating phase of a switched-capacitor (SC) based integrator. The proposed CAZ DSL provides circa 36% lower input-referred noise (IRN) than conventional SC integrator DSL, without the need for an extra timing phase. Circuits are targeted at integrated circuit implementation and designed using a
$0.18~\mu \text{m}$
CMOS technology. The proposed CCIA provides a circa 41.5 dB mid-band gain, consumes a power of
$4~\mu \text{W}$
and has a die area of 0.24 mm2. It achieves an IRN of
$0.73~\mu \text{V}$
rms in the local field potential frequency band and
$2.86~\mu \text{V}$
rms for the action potential frequency band.