Cross-Coupled nFET Preamplifier for Low Voltage SRAM

When supply voltage (VDD) is scaled down to reduce the power consumption in a system-on-chip (SoC), the circuit speed is inevitably degraded. In particular, as SRAM dominates the overall performance of SoC, it is important to prevent the speed degradation of SRAM. This brief proposes a Cross-Coupled nFET preamplifying and precharge circuit (CCN-PP) with the sense amplifier input precharge voltage (VDDSA) boosting circuit to enhance the read speed of SRAM. The cross-coupled nFETs are employed to precharge and preamplify the bit-line voltage for the read operation. The preamplifiying operation of CCN-PP helps in obtaining a larger sense amplifier input voltage difference even with a lower bit-line swing. Consequently, the required bit-line swing for stable sensing is reduced, which improves the speed and power. The simulation results for a 7-nm FinFET at VDD = 0.6 V show a performance improvement of 25.81%–73.14%, energy consumption improvement of 37.17%–72.32%, and area overhead of 10.9% during the read operation.