Fast and Accurate NoC Latency Estimation for Application-Specific Traffics via Machine Learning

Latency is one of the critical performance metrics for Networks-on-Chips (NoCs). When designing an NoC, the designers have to explore enormous design parameters and various traffic patterns, thus a fast and accurate latency estimator is essential to explore the large design space. In this brief, we present an ideal neural network-based methodology for latency estimation in NoCs, especially for application-specific traffics. By inputting the sequence of extracted traffic features and NoC parameters, the neural network model will infer the corresponding average network latency in a fast while accurate way. Instead of training one neural network model for each benchmark from scratch, we adopt transfer learning to train the network model for a new benchmark from another trained one. Experimental results on a set of widely used application-specific NoC benchmarks show that, our method can achieve an average estimation accuracy of 95%, and a 17.1X speedup for large NoCs compared to BookSim2 simulations. Our method can also achieve 20% to 70% improvement in accuracy over the other state-of-art machine learning-based works.

I. Introduction

Networks-on-chip (NoCs) has become the mainstream communication solution for modern multi-core systems. An NoC designer faces at least two key challenges. First, there are a large group of design parameters to tune [1], such as topology, buffer depth, virtual channel and etc. Exploring the design space and finding an optimal solution is an NP-hard problem, facing great challenges [2]. It is essential to develop ideal evaluation methodologies for key performance metrics to accelerate design exploration. Second, when engineers design a new NoC, it’s tedious to go through the design process from scratch. Thus, it is a meaningful but challenging task to re-use the valuable knowledge and experience from the previous design instances to guide the new design.