I. Introduction
Networks-on-chip (NoCs) has become the mainstream communication solution for modern multi-core systems. An NoC designer faces at least two key challenges. First, there are a large group of design parameters to tune [1], such as topology, buffer depth, virtual channel and etc. Exploring the design space and finding an optimal solution is an NP-hard problem, facing great challenges [2]. It is essential to develop ideal evaluation methodologies for key performance metrics to accelerate design exploration. Second, when engineers design a new NoC, it’s tedious to go through the design process from scratch. Thus, it is a meaningful but challenging task to re-use the valuable knowledge and experience from the previous design instances to guide the new design.