A 600-MS/s, 65-dB SNDR, 75-MHz BW Time-Interleaved Noise-Shaping SAR ADC

A time-interleaved noise-shaping (TINS) successive approximation register (SAR) analog-to-digital converter (ADC) for wide bandwidth, high resolution, and low power consumption is proposed. A fully passive switched-capacitor integrator based on a single capacitor and a single-input comparator is adopted in the proposed three-channel structure for 1
^st
-order noise shaping with low power consumption. The SAR conversion is split into coarse and fine conversions to allow noise shaping in the time-interleaved structure to maximize the bandwidth. In addition, a dynamic weight averaging method for three channels is introduced to suppress the effect of capacitor mismatch. The prototype ADC is implemented in a 28-nm CMOS process and achieves a signal-to-noise and distortion ratio of 65.37 dB, a bandwidth of 75 MHz at a sampling rate of 600 MHz, and a power consumption of 4.015 mW with a 1.1 V supply. A Walden figure-of-merit (FoM) of 17.65 fJ/conv.-step and a Schreier FoM of 168.1 dB show that the proposed TINS SAR ADC improves speed and accuracy with good power efficiency.