Non-Volatile and High-Performance Cascadable Spintronic Full-Adder With No Sensitivity to Input Scheduling

The new generation of electronic circuits based on spintronic technology have drawn the attention of researchers in recent years due to their remarkable features, including low-power consumption, non-volatility, and compatibility with the CMOS technology. However, these circuits usually rely on the pre-charge sense amplifier (PCSA), to read the state of the magnetic tunnel junctions (MTJ). The major disadvantage of the PCSAs is the high sensitivity of these circuits to inputs scheduling. It means that if the inputs are not applied to the circuit exactly in the specified time, the generated output will not be valid. This issue causes a serious problem in the ripple carry adders due to their carry propagation. In this brief, a novel structure is proposed which is based on removing MTJ from carry propagation path by adding a post-processing unit. The proposed post-processing unit makes the spintronic adders invulnerable to inputs scheduling. The proposed adder in this brief occupies at least 29% less area. It also offers 40% lower carry propagation delay, and 37% lower power-delay product compared to the efficient state of the art counterpart.